The present invention relates to a method for distributing bits on reliability positions to which a probability is related, that a bit on a reliability position will be transferred correctly. This process is also referred to as priority mapping.
It is an important aspect for communications systems to provide high data transfer rates. In the case of a mobile communications system, this is particularly important for downlink connections; i.e., for connections from a base station to a terminal. For UMTS (Universal Mobile Communications Systems), the so called High Speed Downlink Packet Access (HSDPA) is being developed which provides peak data rates of 10.8 Mbps (Mega bits per second).
The HSDPA data channel is basically an enhancement of the existing UMTS downlink shared channel (DSCH). HSDPA allows to code multiplex different users or mobile stations on up to 15 codes with a spreading factor of 16. The primary multiple access, however, is in the time domain, where different users can be scheduled every transmission time interval (TTI), which corresponds to 3 UMTS slots; i.e., 2 ms. Also, the number of codes allocated to one user can change from TTI to TTI. Depending on the system load and channel conditions, the base station or Node B adapts modulation and code rate for each user. A certain combination of code rate and modulation is referred to as the MCS (Modulation and Coding Scheme) level. The MCS level may change every TTI. It is determined by the base station based on feedback information or channel quality information (CQI) from the user terminal or mobile station, which stems from channel condition measurements. The channel quality information is sent with a periodicity ranging from one to 80 TTIs.
To achieve the high data rates, modulation and coding schemes are used which allow a high information bit rate per code. Therefore, so-called higher modulation techniques are used by which a symbol contains more than 2 bits. One example is 16-QAM (Quadrature Amplitude Modulation). For these modulation techniques, the individual positions for a bit within a symbol are not equally protected. Therefore, there is the ambition to map important bits to well protected positions and less important bits to less protected positions. This is referred to as bit priority mapping and will be detailed below using an example from HSDPA. Furthermore, for channel coding so called turbo codes with rate R=1/3 are used. The rate indicates the ratio of the total number of bits to the number of load or systematic bits.
The HSDPA Coding Chain (cf. FIG. 1 and FIG. 2)
It has been proposed to include bit priority mapping into the current HSDPA coding chain, which will be reviewed in the following with reference to FIG. 1.
The output of a turbo encoder (Turbo Enc) consists, in this case, of three bit classes: systematic bits containing the load or actual information and two groups of parity bits (parity 1 bits and parity 2 bits), which are used for error correction. The data are fed into a first rate matching unit (First Rate Matching) where the parity bits experience a first rate matching. The data are stored in a virtual IR (Incremental Redundancy) buffer (Virtual IR Buffer) before being fed into a second rate matching unit (Second Rate Matching), where all bit classes experience a second rate matching (RM Sys, RM P1_2, RM P2_2).
The respective output of the rate matched bit classes enters a bit priority mapping and interleaving unit (Bit Priority Mapper and Interleaver), where the different input data (that is, the systematic bits and the different groups of parity bits), are introduced into a bit distribution unit (Bit Distribution, DU). After the bit distribution unit DU, before the mapping on a physical channel, the bits are interleaved with interleaving units (according to the Release R99 with a (32×30) Interleaver (R99 Intlv (32×30)).
In the bit distribution unit DU, a so-called priority mapping is performed. By priority mapping the following is understood:
If a modulation scheme higher than QPSK (Quadrature Phase Shift Keying) is used, more bits are coded into a symbol than for QPSK, the different bit positions being differently reliable, as can be seen from FIG. 2, where four 16QAM modulation schemes are depicted. Each of the 16 combinations of the values of real part and imaginary part is referred to as a symbol and represents a bit sequence. The bit-mapping order is i1q1i2q2 for all constellations. The difference between the schemes a-d is only the assignment of the real part value to i1 and i2, and the assignment of the imaginary part value to q1 and q2. It is evident that bit positions, where a value change between 0 and 1 takes places at the borders of a quadrant, are better safeguarded than these, where a value change occurs within a quadrant. As such, depending on the bit mapping order, the MSB (Most Significant Bits), for example, are safeguarded better than the LSB (Least Significant Bits).
Now the problem arises to assign bits to certain positions within a symbol. For turbo encoders, bit classes with different priorities exist; that is, their correct reception is not equally important. These different bit classes are the before mentioned systematic bits with the highest priority and the parity 1 and parity 2 bits with a lower priority. Therefore, systematic bits preferably are assigned to high reliability positions. A detailed description of the distribution method used up until now can be found in the following section.
After the bit distribution, an interleaving process is performed according to the rules implemented in the UMTS standard.
The Bit Distribution Unit (cf. FIG. 3 and FIG. 4)
This section focuses on the bit distribution unit (DU), which again is explained in connection with HSDPA. In [1] it has been proposed to append a bit distribution unit after the HARQ (Hybrid Automatic Repeat Request) functionality that allows bit priority mapping. In FIG. 3, details of the currently-used bit distribution unit are depicted. The bit distribution unit is basically an interleaver where the number of rows corresponds to the number of bits per symbol. The stream of systematic bits is written row-wise first in lines 1 and 2, then the two streams of parity 1 bits and parity 2 bits are written alternatively in the remaining area; i.e., preferably into lines 3 and 4. In case not all systematic bits could be accommodated in lines 1 and 2, systematic bits are also written in lines 3 and 4. This case will be dealt with below.
The output of the data, which are then subject to interleaving, is column-wise.
In [1] the bit distribution unit is described as follows:
Data is read into the interleaver row by row, and [is read] out of the interleaver column by column. To perform priority mapping, the whole stream of systematic bits from the Turbo encoder is read in first, followed by alternating bits from the two parity streams. FIG. 3 illustrates the bit distribution process for 16-QAM using rate [R=]½ code. It may be noted that the alternating parity stream could be read from the bottom right hand corner of the interleaver so that systematic and parity bits do not come from the same symbol.
Thus, for R=½, all systematic bits can be put on high reliability positions and it is not required to design a prosperous distribution on low reliability positions for systematic bits that cannot be accommodated on high reliability positions.
However, having a close look at the bit distribution unit, it is evident, that for R≠1/2, the bit mapping becomes sub-optimal, as now systematic bits are also positioned on low reliability positions; that is, in this example the third and forth row. FIG. 4 shows an example for R=3/4. Again, the input and output of the data is analogous to that described in FIG. 3, apart from the fact that in this case the complete last third of the systematic bits would be mapped to low reliability bit positions in a block-wise fashion; i.e., neighbored bits are arranged in the distribution unit on neighbored positions. For R<1/2, the first parity bits would be mapped to high reliable bit positions in a block-wise fashion. In both cases, the distribution is quite inhomogeneous over the frame, thus creating weak spots in the decoding process. The mapping to high and low reliability probability positions will be detailed further in relation to FIG. 5, which shows a bit distribution unit DU.
The bit distribution unit DU can be represented by an r*c matrix, where r denotes the number of rows and c the number of columns. For 16 QAM modulation, the number of rows is four, as in this case four bits are forming a symbol. The number of columns is chosen such that the desired number of bits can be accommodated. The bits are fed into the matrix row by row beginning with the systematic bits and then continuing with the parity bits. Positions filled with systematic bits are marked by a hatched area. As explained above, the systematic bits might not fit exactly into the first two lines that are mapped to high reliability positions for the 16 QAM modulation, but either cover more than two lines or less than two lines. In combination with the row by row filling modus, this will lead to the above-mentioned block-wise mapping.
Previously, in German application 10150839.5, a bit mapping scheme has been proposed which mitigates this problem by applying a rate matching-like algorithm for bit distribution [2]. This method abolishes the above-mentioned disadvantages of a non-uniform distribution of systematic bits on low reliability positions and parity bits on high reliability positions, respectively, and yields a rather uniform distribution of bits on the respective reliability positions. Therefore, an algorithm similar to the so-called rate matching algorithm is applied to distribute systematic bits (one class of bits) and parity bits on high and low reliable bit streams (i.e., bit streams that will eventually be mapped to high and low reliable bit positions in a modulation).
However, that distribution method required a rather complex process to account for all possible combinations of different modulation schemes, bit rates, coding rates, etc.
To sum up, there have been discussions about how to distribute bits onto the high and low reliability classes for 16 QAM. There are very simple distribution rules as suggested by Samsung (e.g., [6]) and recently by Motorola [1] which, however, cause blocks of systematic bits to be mapped to low reliability positions. This effect has been shown to decrease the performance by independent simulations [2]. There have been other distribution rules proposed, which achieve an even distribution of the low reliability systematic bits within the total set of systematic bits, for example, by using a variant of the rate matching scheme [3]. These rules have been shown to perform in a superior manner, but they are not so simple.